ACM SIGMICRO Newsletter

Recent Papers/Articles

On the limits of program parallelism and its smoothability

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Exploiting instruction-level parallelism with the conjugate register file scheme

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Limitation of superscalar microprocessor performance

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Branch merging for effective exploitation of instruction-level parallelism

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A non-deterministic scheduler for a software pipelining compiler

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Effective compiler support for predicated execution using the hyperblock

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Enhanced region scheduling on a program dependence graph

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An efficient architecture for loop based data preloading

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Stride directed prefetching in scalar processors

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Data path issues in a highly concurrent machine

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A VLIW architecture for optimal execution of branch-intensive loops

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Y-Pipe: a conditional branching scheme without pipeline delays

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Microarchitecture support for dynamic scheduling of acyclic task graphs

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